Power-on reset circuit

ABSTRACT

When the value of a power supply voltage (VDD) becomes a first threshold value or higher, a first start-up circuit ( 20 ) causes a band gap reference circuit ( 10 ) to start a stable operation and a first voltage value (V A ) is output from the band gap reference circuit ( 10 ). When the value of the power supply voltage becomes a second threshold value or higher which is greater than the first threshold, a second start-up circuit ( 40 ) turns on a PMOS transistor (MP 3 ) of a voltage dividing circuit ( 30 ), and a second voltage value (V B ) output from the voltage dividing circuit ( 30 ) becomes a value, which is derived by dividing the value of the power supply voltage according to the resistance ratio of resistors (R 31 , R 32 ). From a voltage comparison circuit ( 50 ), a reset level voltage value is output when the second voltage value (V B ) is smaller than the first voltage value (V A ), and a power-supply voltage level voltage value is output if the second voltage value (V B ) becomes the first voltage value (V A ) or higher.

TECHNICAL FIELD

The invention relates to power-on reset circuits.

BACKGROUND ART

A power-on reset circuit is used in order to secure the stable operationafter starting to supply a power supply voltage in. various electronicdevices. That is, the value of a power supply voltage supplied to anelectronic device gradually increases from a ground potential level atthe start of supply and will soon reach a constant level. If such agradually-increasing power supply voltage value is directly provided toeach circuit in an electronic device, the electronic device may notnormally operate. Then, the power-on reset circuit, in the course ofincreasing of the power supply voltage value, provides a reset levelvoltage value to each circuit in the electronic device when the powersupply voltage value is less than a threshold value, and will provide apower-supply voltage level voltage value to each circuit in theelectronic device when the power supply voltage value becomes thethreshold value or higher, thereby securing the stable operation of theelectronic device.

Such a power-on reset circuit generally includes a bandgap referencecircuit, a voltage dividing circuit, and a voltage comparison circuit asdisclosed in Patent Documents 1 and 2. Even if there is a variation inthe value of a power supply voltage to be supplied or a temperaturevariation, the bandgap reference circuit can output a voltage value witha small variation (hereinafter, referred to as a “first voltage value”).

On the other hand, the voltage dividing circuit includes a firstresistor and a second resistor connected in series between a powersupply voltage terminal to which the power supply voltage is suppliedand a ground terminal, and outputs a voltage value, which is derived bydividing a power supply voltage value according to a ratio of therespective resistance values of the first resistor and second resistor,from a connection point between the first resistor and the secondresistor. That is, the voltage dividing circuit outputs a voltage value(hereinafter, referred to as a “second voltage value”) proportional tothe power supply voltage value.

Then, the voltage comparison circuit receives the first voltage valueoutput from the bandgap reference circuit and the second voltage valueoutput from the voltage dividing circuit, and outputs the reset levelvoltage value when the second voltage value is smaller than the firstvoltage value, and outputs the power-supply voltage level voltage valueif the second voltage value becomes the first voltage value or higher.

CITATION LIST Patent Literature

Patent Document 1: U.S. Pat. No. 5,867,047

Patent Document 2: U.S. Pat. No. 6,847,240

SUMMARY OF INVENTION Technical Problem

In the power-on reset circuit, in the course of increasing of the powersupply voltage value after starting to supply the power supply voltage,at the beginning the second voltage value is greater than the firstvoltage value, and thereafter, for a certain period of time, the secondvoltage value becomes smaller than the first voltage value, and furtherthereafter the second voltage value becomes the first voltage value orhigher. The power-on reset circuit, during a period when the secondvoltage value is smaller than the first voltage value (hereinafter,referred to as a “reset period”), outputs a reset level voltage value toreset each circuit in an electronic device, thereby securing a stableoperation of the electronic device thereafter.

However, in the conventional power-on reset circuits including thosedisclosed in Patent Documents 1, 2, the length of the reset period isunstable. Without a sufficient length of reset period, the stableoperation of the electronic device may not be obtained.

The invention has been made in order to resolve the above-describedproblem and provides a power-on reset circuit capable of stablyproviding a sufficient length of reset period.

Solution to Problem

A power-on reset circuit according to the invention comprises: (1) abandgap reference circuit to which a power supply voltage is supplied,and which outputs a predetermined first voltage value; (2) a firststart-up circuit causing the bandgap reference circuit to start a stableoperation when a value of the power supply voltage becomes a firstthreshold value or higher; (3) a voltage dividing circuit including: aswitch and a first resistor provided in series between a power supplyvoltage terminal to which the power supply voltage is supplied and anoutput terminal; and a second resistor provided between the outputterminal and a ground terminal, the voltage dividing circuit outputtinga second voltage value from the output terminal; (4) a second start-upcircuit which causes the switch of the voltage dividing circuit to closewhen the value of the power supply voltage becomes greater a secondthreshold value or higher which is greater than the first thresholdvalue; (5) a voltage comparison circuit, which receives a first voltagevalue output from the bandgap reference circuit and a second voltagevalue output from the voltage dividing circuit, and outputs a resetlevel voltage value when the second voltage value is smaller than thefirst voltage value, and outputs the power-supply voltage level voltagevalue if the second voltage value becomes the first voltage value orhigher.

In the power-on reset circuit according to the invention, when the valueof the power supply voltage becomes the first threshold or higher, thefirst start-up circuit causes the band gap reference circuit to start astable operation and the predetermined first voltage value is outputfrom the band gap reference circuit. On the other hand, when the valueof the power supply voltage becomes the second threshold or higher whichis greater than the first threshold, the second start-up circuit causesthe switch of the voltage dividing circuit to close, and the secondvoltage value output from the voltage dividing circuit is thus a valuewhich is derived by dividing the power supply voltage according to aratio of the respective resistance values of the first resistor and thesecond resistor. The first voltage value output from the bandgapreference circuit and the second voltage value output from the voltagedividing circuit are input to the voltage comparison circuit. Then, thevoltage comparison circuit outputs the reset level voltage value whenthe second voltage value is smaller than the first voltage value, andoutputs the power-supply voltage level voltage value if the secondvoltage value becomes the first voltage value or higher.

Advantageous Effects of Invention

According to the invention, a sufficient length of reset period can bestably obtained.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a circuit diagram of a power-on reset circuit 1 according toan embodiment.

FIG. 2 is a graph showing the temporal variation of each voltage valuein the power-on reset circuit 1 according to the embodiment.

FIG. 3 is a graph schematically showing the process condition dependenceof each of a threshold voltage V_(thp) of a PMOS transistor MP₂₂, athreshold voltage V_(thn) of an NMOS transistor MN₂₂, and a secondthreshold value V_(th2) which the voltage dividing circuit 30 activates,in the power-on reset circuit 1 according to the embodiment.

DESCRIPTION OF EMBODIMENTS

Hereinafter, with reference to the accompanying drawings, an embodimentof the invention is described in detail. Note that, in the drawings forexplaining the embodiment, the same reference numeral is attached to thesame element, and the repeated explanation thereof is omitted.

FIG. 1 is a circuit diagram of a power-on reset circuit 1 according tothe embodiment. The power-on reset circuit 1 shown in the diagramincludes a bandgap reference circuit 10, a first start-up circuit 20, avoltage dividing circuit 30, a second start-up circuit 40, and a voltagecomparison circuit 50. A common power supply voltage VDD is provided tothese circuits.

The bandgap reference circuit 10 is supplied with a power supply voltageVDD and outputs a predetermined first voltage value V_(A), and includesPMOS transistors MP₁₁-MP₁₃, resistors R₁₁-R₁₇, diodes D₁₀-D_(IN), and anamplifier A₁.

The respective source terminals of the PMOS transistors MP₁₁-MP₁₃ areconnected to a power supply voltage terminal to which the power supplyvoltage VDD is supplied. The respective gate terminals of the PMOStransistors MP₁₁-MP₁₃ are connected to an output terminal of theamplifier A₁.

The drain terminal of the PMOS transistor MP₁₁ is connected to aninverting input terminal of the amplifier A₁ via the resistor R₁₁, andconnected to a ground terminal via the resistor R₁₁ and resistor R₁₂connected in series, and also connected to the ground terminal via thediode D₁₀.

The drain terminal of the PMOS transistor MP₁₂ is connected to anon-inverting input terminal of the amplifier A₁ via the resistor R₁₃,and connected to the ground terminal via the resistor R₁₃ and resistorR₁₄ connected in series, and also connected to one end of the resistorR₁₅. The other end of the resistor R₁₅ is connected to the groundterminal via N diodes (N is an integer of 2 or more) D₁₁-D_(IN)connected in parallel.

The respective resistance values of the resistor R₁₁ and resistor R₁₃are equal to each other. The respective resistance values of theresistor R₁₂ and resistor R₁₄ are equal to each other. The respectiveforward voltages of the diodes D₁₀-D_(IN) vary with the magnitude of acurrent.

The drain terminal of the PMOS transistor MP₁₃ is connected to theground terminal via the resistor R₁₆ and resistor R₁₇ connected inseries. The bandgap reference circuit 10 outputs a voltage value of thedrain terminal of the PMOS transistor MP₁₃ as the first voltage valueV_(A).

The first start-up circuit 20 causes the bandgap reference circuit 10 tostart a stable operation when the value of the power supply voltage VDDbecomes the first threshold value V_(th1) or higher. The first start-upcircuit 20 includes the PMOS transistors MP₂₁, MP₂₂, the NMOStransistors MN₂₁, MN₂₂, and the inverters INV₂₁, INV₂₂.

The respective source terminals of the PMOS transistors MP₂₁, MP₂₂ areconnected to the power supply voltage terminal to which the power supplyvoltage VDD is supplied. The drain terminal of the PMOS transistor MP₂₁is connected to the inverting input terminal of the amplifier A₁ in thebandgap reference circuit 10. The drain terminal of the PMOS transistorMP₂₂ is connected to the drain terminal of the NMOS transistor MN₂₂. Thedrain terminal of the NMOS transistor MN₂₁ is connected to thenon-inverting input terminal of the amplifier A₁ in the bandgapreference circuit 10. The respective source terminals of the NMOStransistors MN₂₁, MP₂₂ are connected to the ground terminal.

The drain terminal of the PMOS transistor MP₂₂ is connected to the gateterminal of the MMOS transistor MN₂₁ via the inverter INV₂₁, and alsoconnected to the gate terminal of the PMOS transistor MP₂₁ via theinverters INV₂₁, INV₂₂ connected in series. The gate terminal of thePMOS transistor MP₂₂ is connected to the output terminal of theamplifier A₁ in the bandgap reference circuit 10. The gate terminal ofthe NMOS transistor MN₂₂ is connected to the power supply voltageterminal.

The on-resistance value of the NMOS transistor MN₂₂ is greater than theon-resistance value of the PMOS transistor MP₂₂. In the NMOS transistorMN₂₂, in order to increase the on-resistance value, a gate length L islong relative to a gate width W, for example, the gate length L is 100times the gate width W.

The voltage dividing circuit 30 includes: the PMOS transistor MP₃ andthe first resistor R₃₁ provided in series between the power supplyvoltage terminal to which the power supply voltage VDD is supplied andthe output terminal: and the second resistor R₃₂ provided between theoutput terminal and the ground terminal, and outputs a second voltagevalue V_(B) from the output terminal.

The source terminal of the PMOS transistor MP₃ is connected to the powersupply voltage terminal to which the power supply voltage VDD issupplied, and the drain terminal of the PMOS transistor MP₃ is connectedto one end of the resistor R₃₁. The other end of the resistor R₃₁ isconnected to the ground terminal via the resistor R₃₂. The connectionpoint between the resistor R₃₁ and the resistor R₃₂ serves as the outputterminal of the voltage dividing circuit 30.

The PMOS transistor MP₃ acts as a switch. That is, when the PMOStransistor MP₃ is in an off state, the switch is opened and the secondvoltage value V_(B) output from the output terminal becomes the groundlevel. When the PMOS transistor MP₃ is in an on state, the switch isclosed and the second voltage value V_(B) output from the outputterminal becomes a voltage value, which is derived by dividing the valueof the power supply voltage VDD according to a ratio of the respectiveresistance values of the resistor R₃₁ and resistor R₃₂.

The second start-up circuit 40 causes the switch of the voltage dividingcircuit 30 to close when the value of the power supply voltage VDDbecomes the second threshold value V_(th2) or higher which is greaterthan the first threshold value V_(th1). The second start-up circuit 40includes the PMOS transistor MP₄, the resistors R₄₁-R₄₃, and theinverter INV₄.

The source terminal of the PMOS transistor MP₄ is connected to the powersupply voltage terminal to which the power supply voltage VDD issupplied. The gate terminal of the PMOS transistor MP₄ is connected tothe power supply voltage terminal via the resistor R₄₁ and alsoconnected to the ground terminal via the resistor R₄₂. The drainterminal of the PMOS transistor MP₄ is connected to the ground terminalvia the resistor R₄₃ and also connected to the gate terminal of the PMOStransistor MP₃ of the voltage dividing circuit 30 via the inverter INV₄.

The voltage comparison circuit 50 receives the first voltage value V_(A)output from the bandgap reference circuit 10 and the second voltagevalue V_(B) output from the voltage dividing circuit 30, and outputs thereset level voltage value when the second voltage value V_(B) is smallerthan the first voltage value V_(A), and outputs the power-supply voltagelevel voltage value if the second voltage value V_(B) becomes the firstvoltage value V_(A) or higher. The voltage comparison circuit 50includes the amplifier A₅ and the inverter INV₅.

The first voltage value V_(A) output from the bandgap reference circuit10 is input to the non-inverting input terminal of the amplifier A₅. Thesecond voltage value V_(B) output from the voltage dividing circuit 30is input to the inverting input terminal of the amplifier A₅. Thevoltage comparison circuit 50 outputs a signal passing from the outputterminal of the amplifier A₅ through the inverter INV₅, as a power-onreset signal POR.

Next, the operation of the power-on reset circuit 1 according to theembodiment is described. FIG. 2 is a graph showing the temporalvariation of each voltage value in the power-on reset circuit 1according to the embodiment. This graph shows the temporal variation ofeach of the power supply voltage VDD supplied to the power-on resetcircuit 1, the first voltage value V_(A) output from the bandgapreference circuit 10, the second voltage value V_(B) output from thevoltage dividing circuit 30, and the power-on reset signal POR outputfrom the voltage comparison circuit 50.

The value of the power supply voltage VDD supplied to the power-on resetcircuit 1 is the ground potential level at the start of supplying thepower supply voltage, and thereafter will gradually increase.

In the bandgap reference circuit 10, for a certain period immediatelyafter starting to supply the power supply voltage, the operation is notstable and the output voltage value V_(A) takes uncertain values betweenthe ground potential level and the power supply voltage level.

When the value of the power supply voltage VDD reaches the firstthreshold value V_(th1), then in the first start-up circuit 20, the NMOStransistor MN₂₂ is turned on and a connection point P₂ between the PMOStransistor MP₂₂ and the NMOS transistor MN₂₂ becomes the groundpotential level. The first threshold value V_(th1) is equal to thethreshold voltage V_(thn) of the NMOS transistor MN₂₂. If the connectionpoint P2 becomes the ground potential level, the output terminal of theinverter INV₂₁ becomes the power supply voltage level and the outputterminal of the inverter INV₂₂ becomes the ground potential level.

Thus, the PMOS transistor MP₂₁ is turned on and the power supply voltagelevel is input to the inverting input terminal of the amplifier A₁ inthe bandgap reference circuit 10. Moreover, the NMOS transistor MN₂₁ isturned on and the ground potential level is input to the non-invertinginput terminal of the amplifier A₁ in the bandgap reference circuit 10.

In the amplifier A₁, if the power supply voltage level is input to theinverting input terminal and the ground potential level is input to thenon-inverting input terminal, then the ground potential level is outputfrom the output terminal. The ground potential level output from theoutput terminal of the amplifier A₁ is applied to the respective gateterminals of the PMOS transistors MP₁₁-MP₁₃, MP₂₂. This turns on each ofthe PMOS transistors MP₁₁-MP¹³, MP₂₂.

If the PMOS transistor MP₁₁ is turned on, a current I₁₁ flows from thepower supply voltage terminal through the source terminal and drainterminal of the PMOS transistor MP₁₁. The current I₁₁ is divided intotwo, and one current flows through the resistor R₁₁ and the resistor R₁₂and the other current flows though the diode D₁₀.

If the PMOS transistor MP₁₂ is turned on, then a current I₁₂ flows fromthe power supply voltage terminal though the source terminal and drainterminal of the PMOS transistor MP₁₂. The current I₁₂ is divided intotwo, and one current flows through the resistor R₁₃ and the resistor R₁₄and the other current flows through the resistor R₁₅ and N diodesD₁₁-D_(IN).

If the PMOS transistor MP₁₃ is turned on, a current I₁₃ flows from thepower supply voltage terminal through the source terminal and drainterminal of the PMOS transistor MP₁₃. The current I₁₃ further flowsthrough the resistor R₁₆ and the resistor R₁₇.

Moreover, the PMOS transistor MP₂₂ of the first start-up circuit 20 isturned on. Since the on-resistance value of the NMOS transistor MN₂₂ isgreater than the on-resistance value of the PMOS transistor MP₂₂, theconnection point P₂ becomes the power supply voltage level. As a result,the respective PMOS transistor MP₂₁ and NMOS transistor MN₂₁ are turnedoff.

The action of the first start-up circuit 20 as described above allowsthe bandgap reference circuit 10 to start a stable operation. In thebandgap reference circuit 10 during the stable operation, a potentialapplied from the amplifier A₁ to the respective gate terminals of thePMOS transistors MP₁₁-MP₁₃ is set so that the connection point P₁₁between the resistor R₁₁ and the resistor R₁₂ and the connection pointP₁₂ between the resistor R₁₃ and the resistor R₁₄ become a potentialequal to each other. Thus, even if the value of the power supply voltageVDD varies, a stable first voltage value V_(A) may be output from theoutput terminal. Moreover, because the temperature dependences of therespective resistance values of the resistor and the diode cancel outwith each other, the stable first voltage value V_(A) may be output fromthe output terminal even if the temperature varies.

Accordingly, the first voltage value V_(A) output from the bandgapreference circuit 10 takes uncertain values between the ground potentiallevel and the power supply voltage level until the value of the powersupply voltage VDD reaches the first threshold value V_(th1). However,the first voltage value V_(A) becomes a stable constant value if thevalue of the power supply voltage VDD reaches the first threshold valueV_(th1).

On the other hand, in the voltage dividing circuit 30 and the secondstart-up circuit 40, for a certain period immediately after starting tosupply the power supply voltage, a connection point P₄₁ between theresistor R₄₁ and the resistor R₄₂ is close to the ground potential leveland the PMOS transistor MP₄ is in an off state. Moreover, a connectionpoint P₄₂ between the PMOS transistor MP₄ and the resistor R₄₃ is alsoclose to the ground potential level and the PMOS transistor MP₃ is in anoff state. Accordingly, the second voltage value V_(B) output from aconnection point P₃₁ between the resistor R₃₁ and the resistor R₃₂ is atthe ground potential level.

If the value of the power supply voltage VDD reaches the secondthreshold value V_(th2), then, in the second start-up circuit 40, thepotential difference between the source terminal and gate terminal ofthe PMOS transistor MP₄ becomes the threshold voltage V_(thp) or higherand the PMOS transistor MP₄ is turned on. The second threshold valueV_(th2) is expressed by a formula “V_(th2=V) _(thp)(R₄₁+R₄₂)R₄₂”. If thePMOS transistor MP₄ is turned on, the potential difference between thesource terminal and gate terminal of the PMOS transistor MP₃ becomes thethreshold value or higher and the PMOS transistor MP₃ is turned on.

Then, if the PMOS transistor MP₃ is turned on, the second voltage valueV_(B) output from the voltage dividing circuit 30 becomes a voltagevalue, which is derived by dividing the value of the power supplyvoltage VDD according to a ratio of the respective resistance values ofthe resistor R₃₁ and the resistor R₃₂, and gradually increasesproportional to the power supply voltage VDD. Neglecting theon-resistance value of the PMOS transistor MP₃, the second voltage valueV_(B) is expressed by a formula “V_(B)=VDD·R₃₂/(R₃₁+R₃₂)”.

As shown in FIG. 2, the first voltage value V_(A) output from thebandgap reference circuit 10 becomes a stable constant value if thevalue of the power supply voltage VDD reaches the first threshold valueV_(th1). On the other hand, the second voltage value V_(B) output fromthe voltage dividing circuit 30 is at the ground potential level untilthe value of the power supply voltage VDD reaches the second thresholdvalue V_(th2), and becomes a value proportional to the power supplyvoltage VDD when the value of the power supply voltage VDD is the secondthreshold value V_(th2) or higher. Provided that the second thresholdvalue V_(th2) is greater than the first threshold value V_(th1).

Accordingly, the magnitude relation between the first voltage valueV_(A) and the second voltage value V_(B) is reversed at a certain timeinstance t₁ after starting to supply the power supply voltage VDD untilthe power supply voltage VDD becomes stable, as a boundary. That is,before the time instance t₁, because the second voltage value V_(B) issmaller than the first voltage value V_(A), the power-on reset signalPOR output from the voltage comparison circuit 50 is at the groundpotential level. After the time instance t₁, because the second voltagevalue V_(B) is greater than the first voltage value V_(A), the power-onreset signal POR output from the voltage comparison circuit 50 is at thepower supply voltage level. In. this manner, the power-on reset circuit1 according to the embodiment can stably provide a sufficient length ofreset period.

Note that it is important that the respective resistors, diodes, PMOStransistors, and NMOS transistors constituting each circuit are designedand manufactured so that the desired characteristics as described abovemay be obtained. Particularly with regard to the PMOS transistors andNMOS transistors, their characteristics vary if the manufacturingconditions vary. It is therefore important that these transistors havesome design margin so that the desired characteristics may be obtainedeven if the manufacturing conditions vary.

FIG. 3 is a graph schematically showing the process condition dependenceof each of the threshold voltage V_(thp) of the PMOS transistor MP₂₂,the threshold voltage V_(thn) of the NMOS transistor MN₂₂, and thesecond threshold value V_(th2) which the voltage dividing circuit 30activates, in the power-on reset circuit 1 according to the embodiment.In order for the voltage dividing circuit 30 to be activated after thebandgap reference circuit 10 is activated, it is important that the PMOStransistors and the NMOS transistors are designed so as to satisfy acondition “V_(th2)>V_(thn)” in a total range of the process conditionvariations, as shown in this graph, even if the manufacturing conditionsvary.

The invention is not limited to the above-described embodiment, butvarious modifications are possible. For example, various configurationsare possible for each circuit constituting the power-on reset circuit 1.

INDUSTRIAL APPLICABILITY

The invention can be applied to the power-on reset circuits for stablyproviding a sufficient length of reset period.

REFERENCE SIGNS LIST

-   1 power-on reset circuit-   10 bandgap reference circuit-   20 first start-up circuit-   30 voltage dividing circuit-   40 second start-up circuit-   50 voltage comparison circuit

1. A power-on reset circuit, comprising: a bandgap reference circuit towhich a power supply voltage is supplied, and which outputs apredetermined first voltage value; a first start-up circuit causing thebandgap reference circuit to start a stable operation when a value ofthe power supply voltage becomes a first threshold value or higher; avoltage dividing circuit including: a switch and a first resistorprovided in series between a power supply voltage terminal to which thepower supply voltage is supplied and an output terminal; and a secondresistor provided between the output terminal and a ground terminal, thevoltage dividing circuit outputting a second voltage value from theoutput terminal; a second start-up circuit which causes the switch ofthe voltage dividing circuit to close when the value of the power supplyvoltage becomes a second threshold value or higher which is greater thanthe first threshold value; and a voltage comparison circuit receiving afirst voltage value output from the bandgap reference circuit and asecond voltage value output from the voltage dividing circuit, andoutputting a reset level voltage value when the second voltage value issmaller than the first voltage value and outputting a power-supplyvoltage level voltage value if the second voltage value becomes thefirst voltage value or higher.